Dielectrically defined optical T-gate for high power GaAs pHEMTs

A dielectrically defined gate process has been developed that uses optical lithography to pattern near quarter micron Tgates. Record output power densities of 2.0 and 1.8 W/mm have been measured at 2 and 10 GHz, respectively. When applied to an X-band MMIC circuit, significantly higher power was measured. The new process offers improved performance and throughput compared to the standard ebeam defined T-gates. Initial results indicate that yield is better as well. These improvements are attributed to passivating the GaAs surface at an earlier step, resulting in fewer surface states and traps. INTRODUCTION A dielectrically defined near quarter micron T-gate process has been developed utilizing optical lithography. This process shows promise for increased yield and throughput compared to conventional quarter micron gate technology defined via electron beam lithography. By using this novel process improved RF performance, specifically higher output power density at 2 and 10 GHz, has been shown. The highest observed output power density (P1dB) at 10 GHz was 1.8 W/mm with 56% PAE and 13.8 dB gain. Additionally, enhancements to the FET DC output characteristics were demonstrated as well as improvements of the measured variances. The developed process defines the trunk and cap of the T-gates in separate steps, which was first described by D Atwood [1] and also employed by Metze et al [2]. Those studies utilized e-beams to write the trunks and reported on the advantages of writing T-gates in two steps, including independent and improved control over the size and placement of the trunk and cap, faster write times and passivation at an earlier step for protection of the surface. The initial motivation for this new process was to improve wafer throughput by eliminating the time consuming e-beam patterning step. However, significant improvements in RF performance and yield have been found which are attributed to the preparation and passivation of the surface at an earlier step. Martinez et al [3] also showed significant RF performance improvement when they switched to a dielectrically defined process and eliminated a surface damaging etchback step. PROCESS The starting epitaxial material is the same used in the standard TriQuint Texas GaAs power pHEMT process. The layers include n+/n GaAs cap layers, and an InGaAs channel sandwiched between Si-pulse-doped AlGaAs layers. Ohmic contacts of Au/Ge/Ni/Au are made to the cap layers followed by implant isolation. A wide recess etch removes the cap layers. In the new flow, processing is identical to the standard quarter micron flow through the ohmic, isolation and wide recess steps. Next, instead of patterning a T-gate profile with an electron beam, a thin PECVD layer of silicon nitride is deposited uniformly across the wafer. Nitride thickness is in the 1000-2000 A range, and the proper surface preparation prior to deposition is believed to be critical to RF performance. Gate stripes are then defined with a Canon I-line 5X stepper that can reliably pattern 0.33 μm in a single layer of photoresist. The patterned photoresist is over-coated with a shrink material, which is then baked and developed away. A small amount of the shrink material remains attached to the resist pattern, reducing the critical dimension (CD), Figure 1a. This a. Gate stripe definition of TRUNK d. Pattern CAP of T-gate e. Recess, evaporate metal and liftoff c. Strip resist b. Low damage dry etch of nitride resist Liftoff resist nitride